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Eriemon/verilog-generator
verilog-generator is a tool for DeepSeek Harness. Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

REVIEW SCORECARD
✓ No risk detected · Automated scan results are for reference only, not an official endorsement
AI DEEP REVIEW
A well-documented, actively maintained Verilog-2001 agent skill with honest verification reporting and multi-platform in
README documents dry-run/JSON installers, automatic backups before writes, and rejection of sources lacking a release receipt, indicating deliberate engineering discipline, though no CI or test suite is visible.
Install scripts are shipped locally in the release package with DryRun preview and backup-before-replace behavior rather than remote download-and-execute, but no explicit permission or secret-handling details are given.
It targets a real and common pain point by turning RTL intent into readable Verilog-2001, reviewing existing designs, and separating static review, simulation, and synthesis results honestly.
Last updated 2026-08-25, not archived, at v2.0.0 with 277 stars, indicating an actively maintained project.
README covers install commands for PowerShell, shell, and batch across Codex, Claude, Gemini, and DeepSeek targets, plus prerequisites, invocation examples, and deliverables, though the exact install command is listed as unknown.
Generated by AI after reading the project README — a decision aid, not an endorsement. Neutral scores are given when information is limited.
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Open repositoryPROJECT TOPICS
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Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
verilog-generator has 277 stars and 17 forks on GitHub, last updated 2026-08-25.
verilog-generator is distributed under the Apache-2.0 license.
verilog-generator is listed in the DSH Universe directory as a tool for DeepSeek Harness. This plugin is listed in the DSH Universe directory and covered by its validation pipeline.
CLASSIFICATION EVIDENCE
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